# ASIC · 日跟踪 · 2026-09-16

> 日期：2026-09-16（Asia/Shanghai）。专题正文：`intel/topics/asic.md`。原料：`/workspace/intel/archive/2026-09-16/`；对照 2026-09-15 日跟踪。

## 摘要

- **新稿 · Astera Labs Leo 2 CXL 智能内存控制器 + Leo X 织物附着内存（ServeTheHome，industry-only-in-09-16）：** Leo 2 E/P：PCIe Gen6 / **CXL 3.2**；通道 2→4；宣称单扩展器最高约 **768GB DDR4** 或 **4TB DDR5**；强调 DDR4 再利用 + RAS（软 ECC/测试引擎）。**Leo X：** 经 Scorpio 交换机挂到机架级加速器织物，主打近加速器 **KV cache**；宣称 TTFT 最高约 **62%**、吞吐约 **22%**（相对 PCIe H200 测例——**厂商/媒体，非 Blackwell 大规模独立核验**）。属 **CXL/互联 ASIC**，非 HCI 节点 SoC。
- **续档 · d-Matrix → NVIDIA NVLink Fusion；Qualcomm Hexagon/Oryon；OpenShift BlueField GA；Infineon 车载 RISC-V 不抬升。**
- **本日无公开「HCI 可售 NPU 一体机 SKU」通稿。**

## 原文摘录

### Astera Labs Leo 2 / Leo X

- 归档：`industry/astera-labs-releases-leo-2-cxl-memory-controllers-and-leo-x-controller-dc4d8160.txt`
- URL：https://www.servethehome.com/astera-labs-releases-leo-2-cxl-memory-controllers-and-leo-x-controller-for-rackscale-fabric-attached-memory/
- 文面：September 15, 2026

> … the Leo 2 family increments that to PCIe Gen6/CXL 3.2…  
> … Doubling the channels doubles the bandwidth and, in the process, doubles the total memory each expander can support, with Astera Labs qualifying up to 768GB of DDR4 or 4TB of DDR5 behind each expander.  
> … Officially, Astera is touting that in their testing they found the Leo X-series improved time to first token by as much as 62% and overall token throughput by 22%.  
> That said, Astera’s testing was against a PCIe-based NVIDIA H200 system rather than a newer Blackwell-based system…

### d-Matrix · 续

- `industry/d-matrix-joins-the-nvidia-nvlink-fusion-platform-f4a94832.txt`  
  > … d-Matrix would bring its next-generation XPUs to the NVLink Fusion platform…