# ASIC 专题日跟踪 · 2026-09-11

> 日期：2026-09-11（Asia/Shanghai）。专题正文：`intel/topics/asic.md`。原料：`archive/2026-09-11/`。

## 摘要

- **新稿 · Qualcomm 下一代 Oryon/Adreno/Hexagon（STH）：** Prime 5 GHz、FlexCache、Adreno Matrix Cores、Hexagon Element Accelerator、共享内存 +50%、INT4 prefill 宣称至 +50%、MoE 约 30B/3B（**厂商自称**）。**手机旗舰 SoC 预热，非 HCI 可售 ASIC SKU。**
- **续档 · Arm Neoverse CSS N4：** 3nm、8–128 核、PCIe Gen7、CMN S4——DPU/服务器子系统参考设计。
- **轻新稿 · Canonical RISC-V@Hot Chips：** RVA23、MicroCloud/K8s 移植——ISA/发行版成熟度，非加速器产品通稿。

## 原文摘录

### Qualcomm Oryon / Hexagon

- 归档：`industry/qualcomm-talks-next-gen-oryon-cpu-adreno-gpu-and-hexagon-npu-a88def6a.txt`  
  URL：https://www.servethehome.com/qualcomm-details-next-gen-oryon-cpu-adreno-gpu-and-hexagon-npu/  
  > … Prime cores… rated at 5 GHz… first mobile CPU to reach that frequency.  
  > The NPU features a new Element Accelerator for transformer operations… context lengths up to 32K…  
  > For INT4 models, Qualcomm reports up to 50 percent prefill uplift…（**厂商自称**）  
  > MoE models up to 30 billion total parameters… roughly 3 billion active parameters…

### Arm Neoverse CSS N4 · 续

- `industry/arm-neoverse-css-n4-launched-for-next-gen-cpus-and-dpus-c9b1b81b.txt`  
  > … 8 to 128 cores per die… up to 128 lanes of PCIe Gen7… N-series… DPUs and network appliances.

### Canonical RISC-V · 轻

- `industry/canonical-evolution-of-enterprise-open-source-risc-v-at-hot-chips-2026-7bbf47cb.txt`  
  > … riscv64 target moved from the RVA20 profile to the RVA23 profile with Ubuntu 25.10.

## 检索范围

- archive/2026-09-11/industry（Qualcomm、Arm、Canonical）；对照 2026-09-10 asic 日跟踪